Universal clock generator using delay lock loop
US6798266B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2003 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | May 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator and method generates a plurality of clocks of different frequencies using a delay lock loop and a sequencer. The delay lock loop receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal. The sequencer receives the delayed clock signals and selects one the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence. The frequency of the output clock signal is controlled by the sequence in which the delayed clock signals are by the sequencer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.