Integrated circuit arrangement with a cascoded current source and an adjusting circuit for adjusting the operating point of the cascoded current source
US6798279B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 27, 2003 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | May 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An integrated circuit arrangement is provided according to the present invention, including a cascoded current source (10) and an adjusting circuit (20) for adjusting the operating point (Vg1, Vg2, Vx) of the cascoded current source (10) by providing gate potentials (Vg1, Vg2) for current source FETs (Q1, Q2), the adjusting circuit having: a reference stage, formed by a pair of reference FETs (M2, M1), which are supplied with reference currents (Iref1, Iref2) in such a way that the current densities in the reference FETs (M2, M1) differ by a predetermined factor (N2), for providing reference gate potentials (Vgs1, Vgs2) at the gates of the reference FETs (M2, M1); a processing stage, for providing an adjustment potential (Vgt1+V1) on the basis of the predetermined factor (N2), which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) plus a predetermined additional voltage (V1), and an output FET (M9), which is connected on the source side to the adjustment potential (Vgt1+V1). Therefore, the present invention provides a circuit for operating point adjustment of a cascoded FET current source, independent of process and temperature variations, which may …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.