Architecture for a faster max* computation
US6798366B1 · kind B1 · utility
2Cited by
4References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2003 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Jul 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/296
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture for a turbo decoder performs a faster max* computation. In this architecture, one or more lookup tables begin processing a digital signal prior to the most significant bit of the digital signal stabilizes. This technique allows processing in the lookup table to be accomplished during a period of time in which processing could not be accomplished previously. As a result, the architecture performs the max* computations at a faster rate than previous architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.