High Speed sense amplifier data-hold circuit for single-ended SRAM
US6798704B2 · kind B2 · utility
10Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Jan 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory with a sense amplifier for high-speed sensing of the signal from a memory cell. The semiconductor memory includes plural memory arrays having plural memory cells, a sense amplifier, and a latch circuit. The memory cells are precharged when a precharge signal is enabled. The sense amplifier has an additional discharge path enabled by the disabled precharge signal to speed up reading data. The latch circuit is turn off by the enabled precharged signal to hold the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.