Daisy chain latency reduction
US6799235B2 · kind B2 · utility
43Cited by
13References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Transmitting data on a serial data transmission path to reduce latency including reading only enough of a device address of a serial data word to determine if the serial data word is addressed to a first device having an address, wherein the serial data word is transmitted across a first link of a first serial data transmission path to the first device and passing the serial data word across a second link of the first serial data transmission path to a second device if the serial data word is not addressed to the first device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.