Memory interface for reading/writing data from/to a memory
US6799246B1 · kind B1 · utility
178Cited by
215References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1997 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Dec 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.