Method and apparatus to control memory accesses
US6799257B2 · kind B2 · utility
14Cited by
17References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Jul 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher and determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core. A front side bus controller switches memory access modes from a minimize memory access latency mode to a maximize memory bus bandwidth mode if a percentage of the memory accesses generated by the hardware prefetcher are used by the out-of-order core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.