Apparatus and method for creating instruction groups for explicity parallel architectures
US6799262B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2000 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Aug 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for creating instruction groups for explicitly parallel architectures is provided. The apparatus and method gather information about the underlying architecture for use in an instruction group creation phase. The information gathered includes the number of each type of execution unit available and the number of bundles that can be dispatched concurrently by the architecture. The instruction group creation of the present invention includes three phases: a first phase for performing initial grouping, a second phase for hosting instructions from further down in the program instruction order if the instruction is not able to be added during the initial grouping phase, and a third optional phase for counting the number of bundles formed to thereby inform a Just-In-Time compiler of the amount of space need to be allocated in a code buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.