Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as instruction operands
US6799266B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | May 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a using instruction and inserting a NOP field into the defining or using instruction. When inserted into the load instruction, the NOP field defines the following latency following the load instruction. When inserted into the using instruction, the NOP field defines the latency preceding the using instruction. In addition, a method for reducing total code size during branching may include the steps of determining a latency following a branch instruction for initiating a branch from a first point to a second point in an instruction stream, and inserting a NOP field into the branch instruction. Further, a method according to this invention may include the steps of locating delayed effect instructions followed by NOPs, such as load or branch instructions, within a code; deleting the NOPs from the code; and inserting a NOP field into the delayed effect instructions. Apparatus according to this invention may include a processor including a code containing a delayed effect instruction, wherein the delayed effect instruction include…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.