Integrated circuit layout method and program for mitigating effect due to voltage drop of power supply wiring
US6799310B2 · kind B2 · utility
5Cited by
1References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Sep 28, 2004 |
| Priority date | — |
| Expiry date | Apr 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit layout method for placing a plurality of cells within a chip comprises a process for sorting the plurality of cells (or function macros) that are to be laid out in order of their delay times (or operation speed margins for macro), placing cells (or macros) having the largest delay times (or smallest speed margin for macro) closer to the peripheral area of the chip, and as the cell delay times get smaller(or the speed margins get larger), placing the relevant cells (or macros) closer to the central area of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.