Method for domain patterning in low coercive field ferroelectrics
US6800238B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Jun 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/3558
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for domain patterning of nonlinear ferroelectric materials. The method seeks to reduce the formation of random and spontaneous micro-domains that typically result during thermal cycling of ferroelectric materials and which leads to patterning defects and degraded performance. In accordance with the invention, a ferroelectric wafer is provided with a conductive layer on the top and bottom surfaces of the wafer. A sufficient bias voltage is applied across the conductive layers to polarize the wafer into a single direction. At least one of the conductive layers is selectively patterned to form a conductive domain template. A sufficient revise bias voltage is then applied to the conductive domain template and a remaining conductive layer to produce the domain patterned structure. According to a preferred embodiment of the invention, the ferroelectric wafer is formed of LiNbO3 or LiTaO3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.