Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET
US6800509B1 · kind B1 · utility
18Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Jun 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for a trench power MOSFET comprises forming a trench on a semiconductor substrate and an oxide and nitride in the trench, etching the oxide and nitride to remain a part of them at the bottom of the trench, and subsequent procedure for the other structure of the trench power MOSFET. Due to the thick insulator formed at the bottom of the trench, the trench power MOSFET is improved by increased voltage endurance and reduced parasitic capacitance, and thereby the cell density is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.