DRAM and MOS transistor manufacturing
US6800515B2 · kind B2 · utility
4Cited by
17References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Nov 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing DRAM cells in a semiconductor wafer including MOS control transistors and capacitors, the source/drain regions and the gates of the control transistors being covered with a protection layer and with an insulating layer, in which the capacitors are formed at the level of openings formed in the insulating layer which extend to the protection layer covering the gates, and in which first capacitor electrodes are connected to source/drain regions of the control transistors by conductive vias crossing the insulating layer and the protection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.