Multiple-bit memory latch cell for integrated circuit gate array
US6800882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Mar 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.