Inter-tile buffer system for a field programmable gate array
US6800884B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate array tiles are arranged in an array of rows and columns. Each of said field programmable gate array tiles comprises a plurality of functional groups and a plurality of interface groups, and a primary routing structure. The primary routing structure is coupled to said functional groups and interface groups and is configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive primary input signals, perform a logic operation, and generate primary output signals. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.