Ball grid array package
US6800948B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Jul 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die. A plurality of wire bonds connect the semiconductor die to the conductive traces of the substrate and an overmold material covers the first surface of the substrate and a remainder of the semiconductor die. A ball grid array is disposed on the second surface of the substrate. Bumps of the ball grid array are in electrical connection with the conductive traces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.