Buffer circuit using low voltage transistors and level shifters
US6801064B1 · kind B1 · utility
31Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Aug 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.