Checkerboard buffer using memory blocks
US6801204B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 17, 2001 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Mar 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices, and where data is stored according to the first order using blocks of memory locations, each block having a number of memory locations equal to a power of 2; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.