Bit reduction using dither, rounding and error feedback
US6801925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2001 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Jan 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49942
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for reducing the number of bits in a K bit value from K to N bits. The circuit generally comprises a first summing circuit, a control circuit, an error feedback circuit, a second summing circuit, and a processor. The first summing circuit may add an error offset value and the N+m MSB's of the K bit value to produce a result data value. The control circuit may generate a dither offset value. The error feedback circuit may receive m LSBs of the result data value and generate an error value in dependence on the m LSBs. The second summing circuit may add the dither offset value and the error value to provide the error offset value. The processor may selectively control generation of the dither offset value and the error value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.