Multiple-thread processor with single-thread interface shared among threads
US6801997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | May 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.