Method and apparatus to directly access a peripheral device when central processor operations are suspended
US6802018B2 · kind B2 · utility
13Cited by
7References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Dec 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for facilitating direct access to computer resources by a peripheral device while the computer's CPU is in a sleeping state. A peripheral device having a circuit to detect the power management state of a central processor, a first interface to couple the device to the central processor if the circuit detects the first power management state, and a second interface to couple the device to a peripheral device if the circuit detects the second power management state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.