Using hardware or firmware for cache tag and data ECC soft error correction
US6802039B1 · kind B1 · utility
31Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Oct 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for error detecting and error recovering in a processor are described. In one embodiment, a system includes at least one cache, one execution unit, and an error detecting and recovering device. The error detecting and recovering device monitors information transferred between the processor components, such as a cache and an execution unit. Once an error is identified, the error detecting and recovering device suspends processor execution. After the error is recovered, the processor execution is resumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.