Efficient layout strategy for automated design layout tools
US6802050B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Apr 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described that involves automatically laying out a circuit structure in software by describing in a software environment the placement of a gate structure relative to a diffusion region. The gate structure has: 1) a pair of gate fingers that project over the diffusion region along a y axis; and, 2) a landing area for receiving multiple contacts from a metal 1 layer. The method also involves running a pair of source fingers at a metal 1 layer over the diffusion area and along the y axis. The pair of source fingers are outside the pair of gate fingers and are an extension of a metal 1 source wire running along an x axis. The method also involves placing a metal 1 gate pad layer over the landing area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.