Non-volatile semiconductor memory device and a method of producing the same

US6803620B2 · kind B2 · utility

Assignee

• SONY GROUP CORPORATION · JP

Inventors

• Hiroyuki Moriya · Minamiashigara, JP
• Toshio Kobayashi · Hino, JP

Key dates

• Filing date: Oct 2, 2002
• Grant date: Oct 12, 2004
• Expiry date: Oct 2, 2022

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/908

Abstract

The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF-overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control-electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2. Since the main regions on facing surfaces of the first control electrodes CG1 and CG2 become forward tapered, conductive residue is not left at the time of processing the second control electrode WL.