Time borrowing using dynamic clock shift for bus speed performance
US6803783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2003 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.