Microprocessor using an interrupt signal for terminating a power-down mode and method thereof for controlling a clock signal related to the power-down mode
US6803784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2003 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Apr 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor uses an interrupt signal for terminating a power-down mode, and a method thereof is used for controlling a clock signal related to the power-down mode. The microprocessor has a clock control unit for controlling whether a clock signal is outputted from a clock generator to the microprocessor, a first control unit which outputs a first control signal to the clock control unit when being level-triggered by an interrupt signal, and a second control unit which outputs a second control signal to the clock control unit for activating a power-down mode. The method includes (a) generating the second control signal to stop the clock generator from outputting the clock signal to the microprocessor, and (b) generating the interrupt signal to trigger the corresponding first control signal for terminating the power-down mode and actuating the clock generator to output the clock signal to the microprocessor after performing step (a).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.