High voltage tolerant output buffer
US6803789B1 · kind B1 · utility
18Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a high voltage tolerant output buffer, which is compatible with a 5-volt input signal on its output node while operating with a 3.3-volt power supply. The high voltage tolerant output buffer includes a NAND gate, a NOR gate, a pair of pull-up transistors, a pair of pull-down transistors, a pair of enable transistors, an inhibit transistor, and a substrate bias circuit. The present invention overcomes the problems due to the degradation of gate-oxide integrity reliability and reduces the fabrication cost by minimizing the chip size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.