Reduced swing charge recycling circuit arrangement and adder including the same
US6803793B2 · kind B2 · utility
12Cited by
11References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Feb 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement uses differential pass transistor logic, a low voltage swing and charge recycling to save power, in which the swing voltage is reduced, but the supply voltage is not reduced, thereby maintaining the transistor device current and avoiding speed degradation. SOI devices including an adder, which uses this circuit arrangement, can avoid the body effect to long pass transistor network and improve the speed at lower supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.