CMOS level shifters using native devices
US6803801B2 · kind B2 · utility
12Cited by
12References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Nov 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.