Electronic component and method for manufacturing the same
US6804103B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2001 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Nov 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic component, in which a chip can be mounted on a certain predetermined place of the package at a high accuracy level, which package having a stepped level-difference in the inner wall of a cavity. The package 13 is provided with a stepped level-difference 26 in the inner wall surface, and an internal contact electrode 14 formed on the upper surface of the stepped level-difference 26. At the bottom of the package 13 is a shield electrode 15, on which a chip 17 is mounted via an adhesion layer 16. The chip 17 and the internal contact electrode 14 are electrically connected by an interconnection wire 19. Location aligning for the chip 17 and the interconnection wire 19, at least either one of these, is conducted by making use of a region 18a, 18b, which is non-electrode portion, provided on the inner bottom surface of the package 13.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.