Addressing of memory matrix

US6804138B2 · kind B2 · utility

Assignee

• Thin Film Electronics ASA · NO

Inventors

• Michael O. Thompson · Ithaca, US
• Per-Erik Nordal · Asker, NO
• Hans Gude Gudesen · Fredrikstad, NO
• Johan Carlsson · Cologne, DE
• Goran Gustafsson · Säter, SE

Key dates

• Filing date: Jul 6, 2001
• Grant date: Oct 12, 2004
• Expiry date: Jul 6, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G09G2320/0209
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto. This timing sequence is provided with a read cycle during which charges flowing between the selected bit line or bit lines connecting thereto are detected and a “refresh/write cycle” during which the polarization of the cells connecting with selected…