Redundant via rule check in a multi-wide object class design layout
US6804808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Apr 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundant via design rule check is preferably performed on multi-wide object class design layouts to ensure that each connection area between two conductive layers has at least a certain number of vias and/or has vias placed appropriately to reduce the risk of via failure due to vacancy concentration of isolated vias. In exemplary embodiments, a redundant via design rule check preferably ensures that for vias placed within a connection area of a metal feature (or within a localized region of a larger metal geometry) that is both greater than a certain width and greater than a certain area in size, the vias are both sufficient in number and/or suitable in their location. Vias located inside a geometry but falling outside a virtual edge of a wide class object may be included to satisfy exemplary rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.