Self-aligned process using indium gallium arsenide etching to form reentry feature in heterojunction bipolar transistors
US6806129B1 · kind B1 · utility
1Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | May 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
Abstract
A method for forming a heterojunction bipolar transistor (HBT) includes forming an etch mask a top layer of the HBT to expose a portion of the emitter cap layer, and selectively etching the exposed portion of the emitter cap layer to (1) form a reentry feature and (2) to expose a portion of the emitter layer. The method further includes selectively etching the exposed portion of the emitter layer to expose a portion of the base layer, and forming a metal layer over the exposed portion of the base layer and the exposed portion of the emitter cap layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.