High precision integrated circuit capacitors
US6806196B2 · kind B2 · utility
5Cited by
9References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Dec 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.