Thermal compliant semiconductor chip wiring structure for chip scale packaging
US6806570B1 · kind B1 · utility
12Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Oct 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thermally compliant multi-layer wiring structure on a semiconductor chip is described. The multi-layer wiring structure incorporates an “empty” or air gap under the interconnect wiring and does not allow any thermally induced strains to be transmitted to the interconnecting solder balls. This design is to be used in chip scale packaging applications where printed circuit technology is used as the next level of package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.