Method and system for clock deskewing using a continuously calibrated delay element in a phase-locked loop
US6806750B1 · kind B1 · utility
12Cited by
8References
18Claims
0Family size
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Key dates
| Filing date | Apr 26, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Apr 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for clock deskewing using a continuously calibrated delay element in a phase-locked loop is provided that includes receiving a feedback signal. A skew select signal is received. The feedback signal is delayed based on the skew select signal to generate a delay output signal. The delay output signal is provided to a phase detector. An external clock signal and the delay output signal are received at the phase detector. A phase detector signal is generated based on the external clock signal and the delay output signal. A skewed clock signal and the feedback signal are generated based on the phase detector signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.