Transconductor tuning circuit
US6806776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Mar 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45682
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transconductor tuning circuit for controlling transconductance of a transconductor. The tuning circuit includes a first MOS (Metal-Oxide Semiconductor) transistor. A source terminal of the first MOS transistor is connected to a power source. A gate terminal and a drain terminal of the first MOS transistor being connected to each other. A gate terminal and a drain terminal of a second MOS transistor being connected. A first input terminal of a first error amplifier is connected to the gate terminal of the first MOS transistor. A second input terminal of the first error amplifier is connected to the gate terminal of the second MOS transistor. The first error amplifier outputs an output signal in form of a bias signal for controlling tuning of the transconductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.