Efficient modulation compensation of sigma delta fractional phase locked loop
US6806780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | May 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.