Integrated circuit for targeted bitlength manipulation for serial data transmission
US6806819B2 · kind B2 · utility
5Cited by
3References
36Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Feb 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03343
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for generating targeted bitlength manipulation of a transmitter for output of a serial datastream. A control unit (5) provides instructions regarding respective partial bits in a form of a partial bit vector (7) depending on bit statuses to be sent, and determines bitlengths for the serial datastream for output (9) to a wire or a signaling converter. The datastream (9) is generated using two partial bit register chains (14a-d, 15a-d), whose serial outputs (16, 17) are connected using a joining gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.