Thin film transistor array panel
US6806937B2 · kind B2 · utility
40Cited by
11References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Dec 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the formation, on a substrate having a display area and a peripheral area, of a gate wire including a plurality of gate lines and gate electrodes in a display area and gate pads in the peripheral area, and of a common wire, including a common signal line and a plurality of common electrodes in the display area. The substrate is fabricated by using less number of steps of photo masks. A photo mask having multiple thickness is used for a photolithography step with less number of masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.