Wireless communication apparatus processing intermittent data
US6807235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2001 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Jan 24, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In order to effectively reduce power consumption of a terminal in a wireless communication apparatus upon packet communication, the wireless communication apparatus has a plurality of signal processing blocks having different signal processing periods; a buffer memory which links the signal processing blocks; and a clock control part which supplies or suspends a clock signal to each block. Each of the signal processing blocks watches whether or not there is data to be processed in the subsequent signal processing block. Based on the watched result, the clock control part controls an operation to supply or suspend the clock signal to the subsequent signal processing block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.