Disconnecting a device on a cache line boundary in response to a write command
US6807590B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/306
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficient bus operations is provided by maintaining alignment with cache line boundaries in response to a write command. A write buffer in a bridge device receives data from any one of a multiple number of bus interfaces. Write buffer management is utilized to monitor on a continuous basis the amount of free space available in the write buffer. When the data in the write buffer approaches the capacity of the write buffer, the system prepares for a potential disconnect of the write initiating device from the bridge device. Data alignment with cache line boundaries is maintained upon disconnect by adjusting the available free space in the write buffer to equal a multiple of a cache line amount of data. The write initiating device is disconnected when the data in the write buffer equals a write buffer full status.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.