Enhanced bus architecture for posted read operation between masters and slaves
US6807593B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2001 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Dec 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic bus architecture for supporting posting of read requests by multiple master devices to multiple slave devices. Sideband signals added to the underlying master bus architecture permit slave devices to receive posted read requests from one or more master devices. The sideband signals are used by the slave devices and associated arbitration logic to enable the slave devices with varying latencies to return requested data to the originating masters when the data becomes available. The sideband slave bus architecture may be applied to enhance performance of AMBA based bus architectures as well as other well-known bus architectures supporting one or more master devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.