Advancing bank pointer in prime numbers unit
US6807619B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Mar 25, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99931
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The cache arrangement includes a cache that may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Associated with each processor is a unique extent increment used to determine a next location for that particular processor when attempting to locate an available slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.