Method of manufacturing an alignment mark
US6809002B2 · kind B2 · utility
4Cited by
13References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | May 28, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon-on-insulator (SOI) substrate has a grid-line region and a circuit region, and includes a silicon substrate having an upper surface, a first insulating layer having an upper surface and a silicon layer, and which has a grid-line region zoning a circuit region. An element isolation region is formed in the silicon layer of the circuit region of the SOI substrate, and an insulating region is formed in the silicon layer of the grid-line region of the SOI substrate. The insulating region and a portion of the first insulating layer located under the insulating region are removed to define a recess in the grid-line region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.