High speed zero DC power programmable logic device (PLD) architecture
US6809550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Oct 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.