Back-drive circuit protection for I/O cells using CMOS process
US6809574B1 · kind B1 · utility
8Cited by
5References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Jul 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a high tolerance I/O interface with over-voltage protection during 5V tolerant mode and back-drive mode, includes pass gate circuitry to isolate the output of the driver circuit and input of the receiver circuit from the pad voltage during stress mode. The gate voltage of the PMOS transistor of the pass gate is charged up to avoid gate oxide breakdown during stress mode. Also, the gate and well of the driver pull-up transistor are charged to NG1 to avoid current flow through the transistor and to its well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.