Ferroelectric semiconductor memory
US6809951B2 · kind B2 · utility
19Cited by
7References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Oct 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric semiconductor memory includes a cell array in which a plurality of ferroelectric memory cells are arranged in a matrix format, and a circuit section. Each memory cell includes a field-effect transistor and a capacitor formed as a gate electrode section of the field-effect transistor and having a stacked structure of metal film/ferroelectric film/metal film. The circuit section selectively executes a read mode, program mode, and erase mode for performing data read, programming, and erase to the memory cells, and a rewrite mode for rewriting data stored in each memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.