Complete refresh scheme for 3T dynamic random access memory cells
US6809979B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2003 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Mar 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh scheme for a semiconductor memory macro that comprises three-transistor dynamic random access memory (3T-DRAM) cells. Similar to an internal refresh operation, an external access command is also interpreted as a read-then-write operation. A clock cycle is partitioned as a plurality of time slots by an internal clock generator. Each time slot is assigned to execute a specific memory cell operations, whereby array idle time typically needed for performing exclusively non-array operations is no longer required. An external access and an internal refresh can be operated sequentially without degrading speed performance. An internal refresh can occur in every clock cycle period to retain the stored data. This clock cycle period is less than the time required for consecutively performing the external access and thereafter the internal refresh upon the completion of the external access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.