PROCESSOR-BASED ARCHITECTURE FOR FACILITATING INTEGRATED DATA TRANSFER BETWEEN BOTH ATM AND PACKET TRAFFIC WITH A PACKET BUS OR PACKET LINK, INCLUDING BIDIRECTIONAL ATM-TO-PACKET FUNCTIONALLY FOR ATM TRAFFIC
US6810039B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2000 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5665
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A processor-based architecture having a processor for facilitating transmission between an ATM port, a first packet port, and a second packet port. The processor-based architecture includes random access memory and a processor coupled to the random access memory and configured to receive ATM cells from the ATM port and first packets from the first packet port and for outputting second packets containing information from both the ATM cells and the first packets on the second packet port. The processor-based architecture includes segmentation-and-reassembly to facilitate bi-directional packet-to-ATM translation functionality. In one embodiment, the processor-based architecture is implemented on a single card and includes dynamic traffic management between ATM and packet traffic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.